Hct138 datasheet

Datasheet

Hct138 datasheet


Recommended operating conditions 9. 1 General description The 74HC138- Q100; 74HCT138- Q100 decodes three binary weighted address inputs. 2 J 0 8; * + Product data sheet Rev. Revision history Document ID Release date 74HC_ HCT138_ Q100 v. Static characteristics Table 6.

Recommended operating conditions Table 5. 6 — 28 hct138 December 5 of 18 Nexperia 74HC138; 74HCT138 3- to- 8 line decoder/ demultiplexer; inverting 8. Could it be that there is a network computer system failure virus connected to the computer , network switching equipment that can not access the cable barrier failure caused it? 74HCT138PW - The 74HC138; 74HCT138 decodes three binary weighted address inputs ( A0 A1 A2) to eight mutually exclusive outputs ( Y0 to Y7). The device features three enable inputs ( E1 E2 E3). In high- performance memory systems, these decoders can.

HCT138 Datasheet free, HCT138 Data sheet, HCT138 PDF, Electronics HCT138, HCT138 manual, Datasheets, HCT138 pdf, datasheet, datenblatt, HCT138, alldatasheet data. This datasheet has been download from:. Philips Semiconductors Product specification. For a complete data sheet, please also download:. The IC06 74HC/ HCT/ HCU/ HCMOS Logic hct138 Family Specifications. We offer finest suppliers for HCT03 HCT03M, HCT03M, HCT04 you can also download the datasheet for HCT03 HCT04. Product hct138 data sheet. Hct138 datasheet. 74HC/ HCT138 3- to- 8 Line Decoder/ demultiplexer; Inverting.

Selling leads from all over the world, Seekic is the world' s biggest IC trading marketplace on the internet. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The ’ HCT138 devices are designed for high- performance memory- decoding or data- routing applications hct138 requiring very short propagation delay times. HC_ HCT138_ Q100 Product. The MC74VHCT138A is an advanced high speed CMOS 3- to- 8 decoder fabricated with silicon hct138 gate CMOS technology. General description The 74HC138; 74HCT138 decodes three binary weighted datasheet address inputs ( A0 A1 A2) to eight mutually exclusive outputs ( Y0 to Y7).
74HC_ HCT138 All information provided in this document is subject to legal disclaimers. 74HC/ HCT165 8- bit Parallel- in/ serial- out datasheet Shift Register. Every output will be HIGH unless E1 hct138 E2 are LOW E3 is HIGH. Hct138 datasheet. NXP Semiconductors Electronic Components Datasheet: 74HCT138 Datasheet 3- to- 8 line decoder/ demultiplexer. HC138 datasheet datasheet, HC138 data sheet, data sheet, HC138 pdf pdf.

Download datasheet for 74 HCT138D- Q100 by NXP Semiconductors N. The 74HC138; 74HCT138 decoder accepts three binary weighted address inputs ( A0 when enabled, A1 hct138 , A3) provides 8 mutually exclusive active LOW outputs ( Y0 to Y7). No Preview Available! General description The 74HC138- Q100; 74HCT138- Q100 decodes hct138 three binary weighted address inputs. HCT03 HCT03M HCT04 datasheet. The 74HC138; 74HCT138 is a hct138 hct138 high- speed Si- gate CMOS device and is pin compatible with Low- power Schottky TTL ( LSTTL).


Datasheet

The ' HC238, ' HCT138, and ' HCT238 are high speed silicon gate CMOS decoders well suited to memory address decoding or data routing applications. Both circuits feature low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL logic. Both circuits have three binary select inputs ( A0, A1 and A2). 74HC138 datasheet, 74HC138 pdf, 74HC138 data sheet, datasheet, data sheet, pdf. The 74HC/ HCT138 are high- speed Si- gate CMOS devices. and are pin compatible with low power Schottky TTL.

hct138 datasheet

They are specified in compliance with JEDEC. The ’ HC138, ’ HC238, ’ HCT138, and ’ HCT238 are high- speed silicon- gate CMOS decoders well suited to memory address decoding or data- routing applications.